1. Field of the Invention
The present invention relates to electrostatic discharge protection techniques for semiconductor integrated circuitry. More particularly, the present invention relates to an electrostatic discharge protection circuit triggered by a floating-base transistor.
2. Description of the Related Art
Electrostatic discharge, ESD hereinafter, may occur everywhere during the phases of testing, assembly, installation, operation, etc., and cause damage to integrated circuits (ICs). Nowadays, several models have been propounded to simulate ESD events, wherein a so-called Human Body Model is generally used to evaluate ESD immunity for integrated circuits because it has a longer ESD pulse period.
Sub-micron CMOS ICs have become increasingly vulnerable to ESD damage due to advanced processes, such as the use of lightly-doped drain structures and clad silicide diffusions. Conventionally, lateral silicon-controlled rectifiers (LSCRs) have been disclosed (for example, in U.S. Pat. No. 5,012,317) as ESD protection circuits for shunting ESD stress. However, the triggering of the conventional lateral silicon-controlled rectifier to activate and thus bypass the ESD stress relies heavily on the P/N junction breakdown between a substrate and a well region formed therein. Due to the fact that both of the substrate and well region are generally provided with a low doping concentration, the trigger voltage of the lateral silicon-controlled rectifier can be up to 30V or more, at which point the ICs may have been adversely affected.
To lower the trigger voltage, U.S. Pat. No. 5,465,189 has disclosed "A LOW VOLTAGE TRIGGERING SEMICONDUCTOR CONTROLLED RECTIFIER" as illustrated in FIG. 1. In the drawing, the SCR is fabricated onto a P-type semiconductor substrate 10, in a predetermined portion of which an N-well region 11 is formed. A P-type doped region 12 and an N-typc doped region 13 are formed within the extent of the N-well region 11 and spaced apart from each other, while an N-type doped regions 14 and a P-type doped region 15 are formed within the extent of the P-type semiconductor substrate 10 and spaced apart from each other. The P-type doped region 12 and the N-type doped region 13 are connected together to an IC pad 1. The IC pad 1 is electrically connected to an internal circuit 2, which is vulnerable to ESD damage and should be protected by the lateral silicon-controlled rectifier. In addition, the N-type doped region 14 and the P-type doped region 15 are connected together to a potential node V.sub.SS, which is generally connected to a ground under normal operation.
Moreover, an N-type doped region 16 is a heavily-doped region, having one portion formed in the N-well region 11 and another portion formed in the P-type semiconductor substrate 10. In other words, the N-type doped region 16 stretches across the P/N junction between the N-well region 11 and the P-type seumconductor substrate 10. Furthermore, a gate structure 17 for this conventional ESD protection circuit is provided from bottom to top, with a gate dielectric layer 18 and a gate electrode layer 19 connected to the V.sub.SS node to overlie a portion of the semiconductor substrate 10 between the N-type doped region 14 and 16.
Correspondingly, the P-type doped region 12, the N-well region 11, and the P-type semiconductor substrate 10 serve as the emitter, base, and collector, respectively, of a PNP bipolar junction transistor 20, while the N-well well region 11, the P-type semiconductor substrate 10, and the N-type doped region 14 serve as the collector, base, and emitter, respectively, of an NPN bipolar junction transistor 21. Referring to FIG. 2, the equivalent circuit diagram of the conventional lateral silicon-controlled rectifier of FIG. 1 is schematically depicted. In the drawing, resistors 22 and 23 designate the respective spreading resistance of the N-well region 11 and the P-type semiconductor substrate 10. Reference numeral 24 represents a metal-oxide-semiconductor field-effect transistor (MOSFET) constituted by the N-type doped regions 14 and 16, the portion of the semiconductor substrate 10 there between, and the gate structure 17.
The conventional ESD protection circuit shown in FIG. 1 has a relatively low trigger voltage but consumes a greater amount of layout area. Moreover, as integrated circuit fabrication advances into the deep sub-micron era, the resistance of the substrate is decreasing, making it more difficult for ESD protection circuits to be triggered.